1. Field of the Invention
This invention relates generally to mini computing systems and more particularly to storage hierarchies having high speed low capacity storage devices coupled to lower speed high capacity devices in a common system bus environment.
2. Description of the Prior Art
The storage hierarchy concept is based on the phenomena that individual stored programs under execution exhibit the behavior that in a given period of time a localized area of memory receives a very high frequency of usage. Thus, a memory organization that provides a relatively small size buffer at the Central Processor Unit (CPU) interface and the various levels of increasing capacity slower storage can provide an effective access time that lies somewhere in between the range of the fastest and the slowest elements of the heirarchy and provides a large capacity memory system that is "transparent" to the software.
Prior art systems use a large capacity store or main memory and a small capacity high speed buffer or cache memory associated with the CU. The cache memory includes a cache directory and a cache data store. In the prior art the CPU requests a data word from both the main memory and cache. If the data word is in cache, then the request of main memory is invalidated. If the data word is not in cache then the requested data word is sent to the CPU and a block of data containing the requested data word is stored in cache. If the CPU updates main memory then cache is updated if the update address is stored in cache. However, if main memory is updated as a result of an interrupt or updated as a result of an input/output operation then cache is not updated but rather a bit is set in the cache directory indicating that the block is invalid.
U.S. Pat. No. 3,588,829 issued to Boland, et al., entitled "Integrated Memory System With Block Transfer to a Buffer Store" teaches that during a channel store, if the addressed location is in Banking Store (BS), the valid bit associated with that location is reset signifying that the data content of the corresponding Main Store (MS) has been changed. U.S. Pat. No. 3,866,183 issued to Lange entitled "Communications Control Apparatus For Use With A Cache Store" and U.S. Pat. No. 3,896,419 issued to Lange, et al., entitled "Cache Memory Store in a Processor of a Data Processing System" which references U.S. Pat. No. 3,840,862 issued to Ready, entitled "Status Indicator Apparatus for Tag Directory in Associative Stores" described the resetting of a full/empty status bit in cache whever the CPU answers an external interrupt signalling that a new program is to be initiated. This essentially empties cache. The high throughput advantages of the cache are therefore delayed until the cache has stored in it a large enough data base to assure an acceptable bit rate.
Copending application Ser. No. 769,617 filed Feb. 17, 1977, entitled "Cache Write Capacity" eliminates the need to flush cache which results in improved throughput by placing the cache in parallel with the backing store and updating cache whenever backing store is updated if cache stores the updated data word. One problem of the disclosed arrangement is that the backing store and cache unit are required to be treated as a single unit. The above arrangement does not permit independent operation of the memory and cache units. Moreover, the above arrangement does not lend itself to a modular system arrangement wherein the memory system includes a plurality of separate memory modules for enabling a number of system units concurrent access to memory for increased throughput.